The present invention, in some embodiments thereof, relates to a ring oscillator test circuit for transistors, and, more particularly, but not exclusively, to testing transistor failure mechanisms using the test circuit.
The reliability of sophisticated semiconductor devices is typically calculated based on the assumption of one dominant failure mechanism. The failure rate is generally determined from published handbook values that are based on accelerated life-tests where zero failures were found. The failure rate is reported as a constant time-independent probability, known as “Failure In Time” (FIT). The FIT value that a manufacturer reports is mathematically the inverse of the mean time-to-fail (MTTF) times 109 failures per part-hour.
Today, there is no qualification standard that accepts failures. Thus, the reported FIT is invariably based on a zero-failure result from a tailored accelerated life test. The test is based on what is assumed to be the dominant failure mechanism, but this is never verified since there were no failures to analyze. The result of this “single potential mechanism” accelerated test (that never caused a failure to occur) results in a misleading assessment of the device reliability when multiple mechanisms exist. This contradiction is recognized in JEDEC Solid State Technology Association Publication JEP 122G Rev. October 2011, which states: “When multiple failure mechanisms and thus multiple acceleration factors are involved, then a proper summation technique, e.g., sum-of-the-failure rates method, is required.” However, neither this standard nor any other handbook suggests what exactly is a “proper summation technique”.
Ring oscillators are well known vehicles for determining the inherent characteristics of a semiconductor electronic device. When measuring low voltage devices, the maximum allowed drain voltage and gate voltages are the same, which makes this a way to test intrinsic device characteristics of a micro-scale or VLSI device.
Newly introduced wide band gap semiconductor power devices are known to exhibit more than a single failure mechanism, such as hot carrier injection, time-dependent dielectric breakdown, negative bias temperature instability (NBTI), single-event gate rupture, electromigration, avalanching and current crowding effects. These mechanisms, as well as solder, packaging and other thermal related failures, may result in failures of newly developed power devices. Now that Gallium nitride (GaN) has been introduced as a new material for high efficiency power conversion, there is a need to determine the reliability of GaN semiconductor devices as well.
Power devices are often tested by incorporating them into actual circuits which may be stressed and tested for performance. However, when power devices are fabricated, the maximum rated drain voltage may be much larger than the maximum gate voltage, making a simple ring-oscillator irrelevant for testing of discrete high voltage or high power devices.
Additional background art includes U.S. Pat. Nos. 6,476,632, 6,653,856 and 6,903,564 and 6,933,731.